The present invention relates to an architecture and a method for reading in parallel and writing in parallel or in series an electronic memory component based on a two-dimensional matrix of binary memory unit cells with two terminals, integrated within a “crossbar” type architecture. According to the invention, this component comprises logic column selection means outside the matrix, which activate at least one column one or more cells of which have to be subjected to read or write processing. It also relates to such a component and method with reading of the state of the cells by differential detection starting from two cells of two different rows, either between a storage column and a constant reference column, or between two rows or two storage columns that correspond to each other in a two-by-two manner.
The invention also relates to such a component in which certain selection means are dedicated exclusively to read operations, and/or in which complementary cells in two complementary columns connected to each other are encoded in a single atomic operation by the same write current.
In the field of rewritable random access computer memories or RAM (Random Access Memory), volatile or non-volatile, a storage unit is generally realized using a grid formed by a series of intersecting rows and columns, where each intersection can have two different states in order to constitute one memory bit. One series, for example the rows, is used to define the different bits inside a memory word; the other series then defining the different words, in this case using the columns.
Generally, there is every benefit to be gained from improvements to known memory technologies, for example in terms of density or reliability or simplicity or flexibility of manufacturing; among other things to keep up with developments in the performances of other electronic or computer components and thus allow the realization of technically homogeneous systems.
The technologies that are currently most widespread, for example DRAM or EEPROM, are provided at each intersection with a transistor, the terminals of which are connected to a row and a column as well as to a third connection. This configuration is sometimes called “1MTJ+1T” meaning “1 magnetic tunnel junction+1 transistor”.
A novel non-volatile RAM memory technology called MRAM is based on the use of cells using the tunnel magnetoresistance (TMR) effect, each connected between a row and a column. Each of these cells comprises a specific stack of two ferromagnetic layers, connected in series with a diode or a transistor according to the writing technology. Depending on the relative direction of the magnetic fields present in these two magnetic layers, parallel or antiparallel, the stack has a different ohmic resistance, thus determining two different states for the cell.
This MRAM technology is non-volatile and has for example the advantage of a good density capability and resistance to environmental conditions. However it has technological implementation difficulties, for example for read reliability due to resistance variation between the two states being fairly small, with a Ron/Roff ratio of the order of 1.5 and in any case less than 3. By comparison, other storage-memory technologies using resistance variation are currently being developed, for example RRAM (Resistive RAM) or MWCM (Molecular Wire Crossbar Memory) technologies, which can locally have a Ron/Roff ratio of the order of 1000 to 10,000.
Memories provided with FIMS (Field Induced. Magnetic Setting) writing technology are now already commercially available in certain advanced fields. Each cell comprises a ferromagnetic stack and a diode or a transistor, and the matrix then has a “1 MTJ +1 D” or “1 MTJ +1T” configuration. Writing is carried out by passing two strong currents through the row and the column concerned, so as to generate two crossed magnetic fields at the two ends of the cell. The role of the diode is to prevent the current from passing through the cell itself. The document U.S. Pat. No 5,640,343 thus presents an operating architecture for an MRAM memory in FIMS technology.
Other MRAM memory writing technologies are currently being developed which have the advantage of much lower consumption: STT (Spin Transfer Torque) or TA STT (Thermally Assisted Spin Transfer Torque) or VIMS (Voltage Induced Magnetic Switching). Unlike the FIMS technologies, these writing technologies require a current to be passed through the cell, up to a current threshold (in STT or up to a voltage threshold (in VIMS), to change the magnetization in one of the layers, for example by spin transfer of the electrons by means of a tunnel effect within the stack, which is called MTJ (Magnetic Tunnel Junction).
The document U.S. Pat. No. 7,764,536, for example, presents an architecture for an STT type operation (in FIGS. 1 to 3), for which it seeks to improve the internal performances of the sense amplifier (Sensing Amplifier) and to reduce its consumption.
In this architecture, the matrix has a “1 MTJ+1T” configuration. Each cell (10 FIG. 1, 110 FIG. 3 in U.S. Pat. No. 7,764,536) comprises an MTJ junction (12 FIG. 1, 112 FIG. 3) in series with a transistor (14 FIG. 1, 114 FIG. 3), and thus comprises three connections:                one end of each cell is connected to a bit line (Bit Line 18 FIG. 1, 103 or 111 FIG. 3 in U.S. Pat. No. 7,764,536),        the other end of each cell is connected to a source line (Source Line 20 FIG. 1, 111 or 103 FIG. 3 in U.S. Pat. No. 7,764,536), and        the grid of the transistor of each cell is connected to a word line (Word Line 16 FIG. 1, 105 FIG. 3 in U.S. Pat. No. 7,764,536).        
In this type of architecture in general, the cells are realized at each intersection of three lines, generally two lines parallel to each other and perpendicular to the third. In this document U.S. Pat. No. 7,764,536, the architecture is presented (FIG. 2) with the bit lines perpendicular to the source lines and to the word lines.
In write mode, each cell is selected and written one after the other. For each cell (10′) selected, the word line (16′) which corresponds thereto is activated to turn on the transistors of the cells of this word. A bit selector (34) selects the bit line and the source line of this cell and connects them to a write driver (40), which applies to them a write voltage oriented in one direction or in the other according to the write state.
In read mode, each cell (10′) is selected and read one after the other. For each cell (10′) selected, the corresponding word line (16′) is activated to turn on the transistors of all the cells of this word. The bit selector (34) selects the bit line and the source line of this cell and connects them to a sense amplifier (Sense Amplifier 38). This amplifier carries out a reading of the resistance of the selected cell (10′) by comparison with the resistance of a reference cell (Reference Generator 26) received by a reference line (Reference Line 46).
This MRAM architecture with a write current passing through the cell could however be improved, in particular in terms of greater density, better reliability, and/or greater manufacturing simplicity or flexibility.
The document U.S. Pat. No. 6,795,336 (Kim et al.) for example uses a specific structure of the cells with one of the three connections linked to a plate (CP) common to several cells.
The document EP 1 321 944 uses cells integrated within a matrix, and each comprising several junctions managed by the same selection transistor.
The presence of these three connections per cell nevertheless also represents a constraint that limits the possibility of increasing the density. Furthermore, the logic management circuits of the cells represent a significant space requirement, typically equivalent to that of the matrix that they manage.
The document U.S. Pat. No. 7,715,228 proposes a different architecture that can be used in SU, which uses multipole analog switches situated at the end of each of the rows and columns of the cell grid or matrix.
In order to select a cell to be written, these switches connect the row selected to the nominal write voltage and the column selected to the ground; whereas the rows not selected are connected to a first intermediate voltage and the columns not selected are connected to a second intermediate voltage. The cells not selected thus only receive a current lower than the write current, and do not change state during the writing of the cell selected.
In order to select a cell to be read, these switches connect its row to the nominal read voltage and its column to the ground; whereas the other rows are left open and the other columns for their part are also connected to the read voltage.
This technique has drawbacks because the cells not selected are still subjected to a certain voltage, which makes the range of voltage values more difficult to adjust, and can also be a source of interference.
Furthermore, each row and column end has a high space requirement, which adversely affects the density of the overall circuit, since it has to be provided with a multipole analog switch as well as four connections including three different voltage supplies.
The fitting of such a large number of analog components within a logic circuit can moreover be a source of additional difficulties of integration and compatibility.